1. Technical Field
This invention relates generally to semiconductor technology and more particularly to control method and apparatus for flash memory devices.
2. Related Art
As data storage capacity required in various mobile electronics and embedded devices increases, demands for flash memory type EEPOMs (Electrically Erasable Programmable Read Only Memory) is on the increase. Flash memory is used for easy and fast information storage in devices like digital cameras, portable MP3 players and home video game consoles. It is used more as a hard drive than as RAM. Advantages of the flash memory among other include: cheaper than SRAM; faster than hard disk, no moving part, and maintaining data without power supply. Typical applications of flash memory include PCMCIA flash-storage cards, MP3 players, and digital voice recorders. Key application requirements are high density, low cost per byte, and tolerance for storage errors. Flash memory stores program code for an embedded processor, such as a high-end 32-bit, RISC CPU used in a router or a DSP used in a cellular phone.
In a flash memory, a write or program operation is always preceded by an erase operation even when the location to which data is to be written is a part of page or sector in a memory block. Further, flash memory has different erase size and write (or program) size. Accordingly, writing data into the flash memory is time-consuming and the life span of the memory decreases according to an increase of erase-write cycles.
In conventional flash memory, the erase operation is performed in a various methods. For example, the memory is divided into blocks (or sectors) that are each separately erasable, but only one at a time. After selecting the desired block and temporarily moving data in such block to RAM, the designated area is erased. The data in RAM is then restored into the memory by programming back into the device. In more improved prior art, the flash memory is divided into sectors where all cells within each sector are erasable together. Each sector can be addressed separately and selected for erase. This makes possible to select any combination of sectors for erase together and allows for a faster system erase.
However, in prior arts there still exist additional and unnecessary operations, which causes lowering of the performance the memory system and delay in operational speed. For instance, write operation of the conventional flash memory as shown in FIG. 1 is as follows.
(1) Flash memory controller 20 receives from a host 10 a logical address LA for designating location to which data is to be written.
(2) Memory controller 20 translates LA into a physical address PA.
(3) Data back-up to a buffer perfroms to areas in a memory block that includes the translated PA but excepting data to be written. For example, the memory array 30 in FIG. 1 has a plurality of memory units or banks (30A, 30B, . . . , 30N), with each unit having a plurality of memory blocks (30A1, 30A2, . . . , 30AM; 301B, 30B2, . . . , 30BM; . . . ; 30N1, 30N2, . . . , 30NM), and each of the memory block comprises a number of sectors or pages 32. Supposing that a physical address to which data is to be written includes a page 36A in a first memory block 30A1 of the first memory 30A as well as a page 36B in a second memory block 30B2 of the second memory 30B, data in pages to which no data is written (i.e., pages 34A and 34B) are moved to the data buffer and data backup is carried out before writing data into the pages 36A and 36B.
(4) Erase blocks that includes the pages addressed by the logical address (in this case, blocks 30A1 and 30B2).
(5) Memory controller 20 receives data to be written from the host 10.
(6) Memory controller 20 programs data delivered from the host 10 into the location (in this case pages 36A and 36B) addressed by the logical address.
(7) Data backed-up at the previous step (3) is restored from the data buffer in the memory controller 20 to the original location (e.g., pages 34A and 34B).
In this conventional system, the operations for erasing all the appropriate blocks and for programming data into the designated locations are inevitable. However, such operations of data backup and data restoration are additional ones arising from the properties of the flash memory. As a result, particularly in case that program size and erase size (e.g., memory block) are greatly different, lots of time should be consumed in the additional data backup and restoring operations. Moreover, the data backup operation entails a data read operation.
One of most significant technical challenges in flash memory is to increase the data read and write speed. For doing this, techniques such as for optimization of software or increase of frequency (e.g., speed-up the operation of a memory control device that processes data from the host system, or improve the speed of an interface between the memory control device and the flash memory), or parallel interconnection of multiple flash memories have been employed in prior art. However, the prior methods have limitations due to e.g., the increase of current and the construction of the host system or the flash memory control system.